The website 'Verilog Master' is our contribution to the community of Verilog learners, which includes students and industry professionals from all over the world. Our work is entirely original and every article has been crafted by the members of the team.Verilog is a Hardware Description Language (HDL) used to model and design electronic circuits and devices. It is unanimously used in many institutions worldwide and the number of online learning resources on Verilog is very less as compared to the resources available for software programming languages like Python and C. Scarcity of reliable online resources on Verilog is one of the main reasons we thought of developing this website. We wish to make our OER as a teaching aid for teachers and a learning aid for students worldwide. It also aims to provide help to industry professionals who use Verilog on a day to day basis. Our team is a set of 4 highly enthusiastic undergraduate students from NITW, India who have learnt the Verilog language and are in the process of polishing their skills further. Every member contributed to the content development, Verilog coding, website development, graphic designing, layout of the website, management of the content and distribution into subtopics. With a goal to provide thorough understanding of design techniques and their implementation in Verilog, we have tutorials ranging from basic gates to advanced registers and memory elements. The content is unique, non plagiarised and authentic. For the current deployment we have categorized the tutorials as: Basics of Verilog, Levels of Abstraction and Combinational Circuits. For further sections, we plan to add: Sequential Circuits and Advanced Arithmetic Units. Presently, the website is entirely functional and we are in the process of adding new tutorials to our local repository. Our aim is to make VerilogMaster a one stop platform for all things Verilog! Our goal is to publish tutorials on numerous different logic blocks and arithmetic circuits which can be coded using Verilog. Once we achieve the milestone of a decent number of articles on Verilog, then we wish to include content on SystemVerilog (SV) as well. SV is another high level language used for similar modeling but it provides increased functionality.
