Material Detail

This is an example which demonstrates the application of the LOGITHERM module of SISSSI. We have designed a simple, 8-bit binary counter. In order to increase the event density, thus the dissipation density we connected an inverter-chain of 20 inverters and further 20 two-input AND gates to each output bit of the counter. The final circuit contained altogether 343 standard cells and the necessary number if I/O pads. The counter was driven by a tex2html_wrap_inline956 clock and the tex2html_wrap_inline860 simulation window was tex2html_wrap_inline960 The execution time of one logi-thermal simulation cycle on a SUN Sparc 20 workstation was 34.5 sec. During this time Verilog has executed 146180 events (state transitions) and this execution time also includes a steady-state THERMANAL run. Fig. 15 presents the temperature distribution after one simulation cycle. Since the logic state transitions are the most frequent at the LSB of the counter, an increased temperature is expected at the corresponding cells of the layout. In Fig. 15. the cells of the lowermost bit of the counter can be clearly seen due to their increased temperature.

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