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Material Detail

SIMULACION FSM: Generación del reset

SIMULACION FSM: Generación del reset

Con este objeto se caracteriza la temporización correcta de la señal de reset y se desarrollar un ejemplo sencillo de banco de pruebas en Verilog con dicha señal de reset
Keywords:
Task, Verilog, Simulación, Reset, FSM
Disciplines:
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More about this material

Material Type:
Animation
Date Added to MERLOT:
September 6, 2019
Date Modified in MERLOT:
September 6, 2019
Author:
Submitter:
RIUNET Universitat Politècnica de València
Primary Audience:
High School, College General Ed, College Lower Division, College Upper Division, Graduate School
Technical Format:
Video, Website
Mobile Compatibility:
Blackberry, iOS (Apple), Windows Mobile, Android
Language:
Spanish
Cost Involved:
No
Source Code Available:
No
Accessibility Information Available:
No
Creative Commons:
Creative Commons License
This work is licensed under a Attribution-ShareAlike 4.0 International

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